179 search results - page 29 / 36 » A Memory Management System Optimized for BDMPI's Memory and ... |
EUROSYS
2009
ACM
14 years 5 months ago
2009
ACM
The backends of today’s Internet services rely heavily on caching at various layers both to provide faster service to common requests and to reduce load on back-end components. ...
ANCS
2007
ACM
14 years 24 days ago
2007
ACM
There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection...
EUROPAR
2009
Springer
14 years 20 days ago
2009
Springer
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
IWOMP
2007
Springer
14 years 2 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
ICCS
2009
Springer
14 years 3 months ago
2009
Springer
Irregular and sparse scientific computing programs frequently experience performance losses due to inefficient use of the memory system in most machines. Previous work has shown t...