383 search results - page 17 / 77 » A Methodology for High Level Power Estimation and Exploratio... |
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the lo...
ISQED
2007
IEEE
14 years 2 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
TCAD
2008
13 years 7 months ago
2008
Abstract--Thermal issues are fast becoming major design constraints in high-performance systems. Temperature variations adversely affect system reliability and prompt worst-case de...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
Rapid evaluation and design space exploration at the algorithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation meth...