1609 search results - page 318 / 322 » A Microeconomic Scheduler for Parallel Computers |
CF
2006
ACM
14 years 1 months ago
2006
ACM
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
SIGARCH
2008
13 years 7 months ago
2008
As multicore architectures gain widespread use, it becomes increasingly important to be able to harness their additional processing power to achieve higher performance. However, e...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
To sustain emerging data-intensive scientific applications, High Performance Computing (HPC) centers invest a notable fraction of their operating budget on a specialized fast sto...
POPL
2010
ACM
14 years 2 months ago
2010
ACM
Message-passing is an attractive thread coordination mechanism because it cleanly delineates points in an execution when threads communicate, and unifies synchronization and comm...
ICDCSW
2003
IEEE
14 years 24 days ago
2003
IEEE
It is a challenging task to provide Quality of Service (QoS) control for a shared high-speed downlink packet access (HSDPA) wireless channel. In this paper, we first propose a ne...