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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
14 years 22 days ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
ASPLOS
2008
ACM
14 years 22 days ago
Concurrency control with data coloring
Concurrency control is one of the main sources of error and complexity in shared memory parallel programming. While there are several techniques to handle concurrency control such...
Luis Ceze, Christoph von Praun, Calin Cascaval, Pa...
AUSAI
2008
Springer
14 years 22 days ago
L-Diversity Based Dynamic Update for Large Time-Evolving Microdata
Data anonymization techniques based on enhanced privacy principles have been the focus of intense research in the last few years. All existing methods achieving privacy principles ...
Xiaoxun Sun, Hua Wang, Jiuyong Li
CICLING
2008
Springer
14 years 22 days ago
Semantic and Syntactic Features for Dutch Coreference Resolution
We investigate the effect of encoding additional semantic and syntactic information sources in a classification-based machine learning approach to the task of coreference resolutio...
Iris Hendrickx, Véronique Hoste, Walter Dae...
CIKM
2008
Springer
14 years 22 days ago
Error-driven generalist+experts (edge): a multi-stage ensemble framework for text categorization
We introduce a multi-stage ensemble framework, ErrorDriven Generalist+Expert or Edge, for improved classification on large-scale text categorization problems. Edge first trains a ...
Jian Huang 0002, Omid Madani, C. Lee Giles
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