Sciweavers

389 search results - page 39 / 78
» A Model for the Coanalysis of Hardware and Software Architec...
Sort
View
CODES
2009
IEEE
14 years 3 days ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
MSE
2002
IEEE
122views Hardware» more  MSE 2002»
14 years 9 days ago
Modeling and Analyzing SMIL Documents in SAM
A composite multimedia object has specific timing relationships among the different types of component media. Coordinating the real-time presentation of information and maintaini...
Huiqun Yu, Xudong He, Shu Gao, Yi Deng
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
14 years 1 months ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...
HPCA
2002
IEEE
14 years 7 months ago
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach
Power dissipation has become one of the most critical factors for the continued development of both high-end and low-end computer systems. The successful design and evaluation of ...
Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary J...
IPPS
2003
IEEE
14 years 20 days ago
Targeting Tiled Architectures in Design Exploration
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas...