14 search results - page 3 / 3 » A Multiple Blocks Fetch Engine for High Performance Supersca... |
WMPI
2004
ACM
14 years 27 days ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
ISCAPDCS
2004
13 years 8 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
ISCA
2002
IEEE
14 years 12 days ago
2002
IEEE
This paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressiv...
ISPASS
2003
IEEE
14 years 22 days ago
2003
IEEE
Achieving high performance in cryptographic processing is important due to the increasing connectivity among today’s computers. Despite steady improvements in microprocessor and...