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» A Network Memory Architecture Model and Performance Analysis
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JPDC
2010
106views more  JPDC 2010»
13 years 7 months ago
Feedback-directed page placement for ccNUMA via hardware-generated memory traces
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
Jaydeep Marathe, Vivek Thakkar, Frank Mueller
IWNAS
2008
IEEE
14 years 3 months ago
Software Barrier Performance on Dual Quad-Core Opterons
Multi-core processors based SMP servers have become building blocks for Linux clusters in recent years because they can deliver better performance for multi-threaded programs thro...
Jie Chen, William A. Watson III
DAC
1997
ACM
14 years 1 months ago
Remembrance of Things Past: Locality and Memory in BDDs
Binary Decision Diagrams BDDs are e cient at manipulating large sets in a compact manner. BDDs, however, are inefcient at utilizing the memory hierarchy of the computer. Recent ...
Srilatha Manne, Dirk Grunwald, Fabio Somenzi
FMCAD
2000
Springer
14 years 23 days ago
Scalable Distributed On-the-Fly Symbolic Model Checking
Abstract. This paper presents a scalable method for parallel symbolic on-the-fly model checking in a distributed memory environment. Our method combines a scheme for on-the-fly mod...
Shoham Ben-David, Tamir Heyman, Orna Grumberg, Ass...
TJS
2008
95views more  TJS 2008»
13 years 9 months ago
Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
Akshat Verma, Sandeep Sen