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» A Network Memory Architecture Model and Performance Analysis
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ICPP
2006
IEEE
14 years 3 months ago
Parallel Algorithms for Evaluating Centrality Indices in Real-world Networks
This paper discusses fast parallel algorithms for evaluating several centrality indices frequently used in complex network analysis. These algorithms have been optimized to exploi...
David A. Bader, Kamesh Madduri
SDL
2003
147views Hardware» more  SDL 2003»
13 years 10 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
CEE
2006
94views more  CEE 2006»
13 years 9 months ago
Study and performance analysis of transport layer mechanisms applied in military radio environment
The need for reliable data communication performed in critical conditions and the respect of real-time constraints is an open issue in radio-military networks, where fixed and nom...
Tomaso de Cola, Mario Marchese
ISCA
2007
IEEE
142views Hardware» more  ISCA 2007»
14 years 3 months ago
MetaTM//TxLinux: transactional memory for an operating system
This paper quantifies the effect of architectural design decisions on the performance of TxLinux. TxLinux is a Linux kernel modified to use transactions in place of locking prim...
Hany E. Ramadan, Christopher J. Rossbach, Donald E...
MOBIHOC
2009
ACM
14 years 9 months ago
Delay and effective throughput of wireless scheduling in heavy traffic regimes: vacation model for complexity
Distributed scheduling algorithms for wireless ad hoc networks have received substantial attention over the last decade. The complexity levels of these algorithms span a wide spec...
Yung Yi, Junshan Zhang, Mung Chiang