This paper presents a hybrid shared memory architecture which combines the scalability of a multistage interconnection network with the contention reduction benefits of coherent c...
This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance require...
Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Stee...
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
The last years have seen an increasing, albeit restricted simulation of large-scale networks on shared memory parallel platforms. As the complexity of communication protocols and ...
In distributed and mobile systems with volatile bandwidth and fragile connectivity, non-functional aspects like performance and reliability become more and more important. To forma...