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    ACM
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    Construction of realistic gate sizing benchmarks with known optimal solutions
    12 years 6 months ago
    Construction of realistic gate sizing benchmarks with known optimal solutions
    Download  vlsicad.ucsd.edu
    Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
    Andrew B. Kahng, Seokhyeong Kang
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