62 search results - page 10 / 13 » A Non-binary Parallel Arithmetic Architecture |
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
Leveraging the power of nowadays graphics processing units for robust power grid simulation remains a challenging task. Existing preconditioned iterative methods that require inco...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
ASPDAC
2007
ACM
14 years 2 months ago
2007
ACM
Logic synthesis has made impressive progress in the last decade and has pervaded digital design replacing almost universally manual techniques. A remarkable exception is computer ...
TVLSI
2008
13 years 10 months ago
2008
With the density of FPGAs steadily increasing, FPGAs have reached the point where they are capable of implementing complex floating-point applications. However, their general-purpo...