62 search results - page 3 / 13 » A Non-binary Parallel Arithmetic Architecture |
HPCA
2000
IEEE
14 years 9 months ago
2000
IEEE
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
CASES
2009
ACM
14 years 8 months ago
2009
ACM
2's complement number system imposes a fundamental limitation on the power and performance of arithmetic circuits, due to the fundamental need of cross-datapath carry propaga...
VLSID
2002
IEEE
15 years 5 months ago
2002
IEEE
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit ...
ASAP
1996
IEEE
14 years 9 months ago
1996
IEEE
We propose in this paper a new algorithm and architecture for performing divisions in residue number systems. Our algorithm is suitable for residue number systems with large modul...
VLSISP
2002
14 years 4 months ago
2002
Abstract. This paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband proc...