522 search results - page 103 / 105 » A Note on Designing Logical Circuits Using SAT |
FPGA
2006
ACM
13 years 10 months ago
2006
ACM
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
DT
2000
13 years 6 months ago
2000
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...
CODES
2008
IEEE
14 years 1 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
TCAD
2010
13 years 1 months ago
2010
Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical des...
WSC
2001
13 years 8 months ago
2001
In this paper, the selection of a BASE Case was every bit as important as the simulation itself. The production team had been familiar with simulations and had used their results ...