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HPCA
2009
IEEE
14 years 8 months ago
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonia...
CSREAESA
2003
13 years 9 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
ISI
2006
Springer
13 years 7 months ago
Synergy: A Policy-Driven, Trust-Aware Information Dissemination Framework
Information dissemination is of vital importance in today's information-centric world. However, controlling the flow of information across multiple security domains is a probl...
Ragib Hasan, Marianne Winslett
HPN
1994
13 years 9 months ago
Fast Connection Establishment in the DTM Gigabit Network
Dynamic synchronous Transfer Mode (DTM) is a new protocol suite based on synchronous fast circuit switching. The DTM network is based on bandwidth reservation and supports dynamic...
Per Lindgren, Christer Bohm
CAL
2010
13 years 5 months ago
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem