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» A Novel Superscalar Architecture for Fast DCT Implementation
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JSAC
2008
91views more  JSAC 2008»
13 years 7 months ago
A novel receiver architecture for single-carrier transmission over time-varying channels
In this paper, we present a single-carrier transceiver for rapidly time-varying channels, where the equalization step is implemented in the frequency domain. When the channel abide...
Zijian Tang, Geert Leus
ARVLSI
1999
IEEE
112views VLSI» more  ARVLSI 1999»
14 years 1 days ago
Architectural Considerations for Application-Specific Counterflow Pipelines
Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific processors are especially promising for ...
Bruce R. Childers, Jack W. Davidson
CSREAESA
2006
13 years 9 months ago
Design and Implementation of SoPC with Multi-Bus on a Chip
SoPC (System on a Programmable Chip) is one important kind of SoC solution based on PLD (Programmable Logic Device). At the same time, PBD (Platform-based Design) has become popul...
Fangjun Jian, Jizhong Han, Chengde Han, Qin Zhang,...
HPCA
2009
IEEE
14 years 8 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
EWSN
2007
Springer
14 years 7 months ago
RIDA: A Robust Information-Driven Data Compression Architecture for Irregular Wireless Sensor Networks
Abstract. In this paper, we propose and evaluate RIDA, a novel informationdriven architecture for distributed data compression in a sensor network, allowing it to conserve energy a...
Xuan Thanh Dang, Nirupama Bulusu, Wu-chi Feng