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» A Parallel Hardware Architecture for Image Feature Detection
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MVA
1992
173views Computer Vision» more  MVA 1992»
13 years 9 months ago
VLSI Optimal Edge Detection Chip: Canny-Deriche Filter
This paper presents the design of an ASIC intended for optimal edge detection of blurred and noisy 2-D images. The chip has a parallel and pipelined architecture which processes a...
Mohamed Akil, Nizar Zarka
CAMP
2005
IEEE
14 years 2 months ago
Real-Time Low Level Feature Extraction for On-Board Robot Vision Systems
Abstract— Robot vision systems notoriously require large computing capabilities, rarely available on physical devices. Robots have limited embedded hardware, and almost all senso...
Roberto Pirrone, Giuseppe Careri, F. Saverio Fabia...
ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
14 years 2 months ago
Error resilient content-based image authentication over wireless channel
—The pervasive distribution of digital images triggers an emergent need of authenticating degraded images by lossy compression and transmission. This paper proposes a robust cont...
Shuiming Ye, Qibin Sun, Ee-Chien Chang
CGO
2003
IEEE
14 years 1 months ago
Dynamic Trace Selection Using Performance Monitoring Hardware Sampling
Optimizing programs at run-time provides opportunities to apply aggressive optimizations to programs based on information that was not available at compile time. At run time, prog...
Howard Chen, Wei-Chung Hsu, Dong-yuan Chen
ECOOP
2008
Springer
13 years 10 months ago
Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary
Abstract. The paradigm shift in processor design from monolithic processors to multicore has renewed interest in programming models that facilitate parallelism. While multicores ar...
Shan Shan Huang, Amir Hormati, David F. Bacon, Rod...