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» A Parallel Hardware Architecture for Image Feature Detection
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DSN
2005
IEEE
14 years 2 months ago
Checking Array Bound Violation Using Segmentation Hardware
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...
Lap-Chung Lam, Tzi-cker Chiueh
ICIP
2002
IEEE
14 years 10 months ago
Hybrid and parallel face classifier based on artificial neural networks and principal component analysis
We present a hybrid and parallel system based on artificial neural networks for a face invariant classifier and general pattern recognition problems. A set of face features is ext...
Peter V. Bazanov, Tae-Kyun Kim, Seok-Cheol Kee, Sa...
ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
14 years 3 months ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...
CCS
2011
ACM
12 years 8 months ago
MIDeA: a multi-parallel intrusion detection architecture
Network intrusion detection systems are faced with the challenge of identifying diverse attacks, in extremely high speed networks. For this reason, they must operate at multi-Giga...
Giorgos Vasiliadis, Michalis Polychronakis, Sotiri...
DAGM
2008
Springer
13 years 10 months ago
Sliding-Windows for Rapid Object Class Localization: A Parallel Technique
Abstract. This paper presents a fast object class localization framework implemented on a data parallel architecture currently available in recent computers. Our case study, the im...
Christian Wojek, Gyuri Dorkó, André ...