Sciweavers

471 search results - page 81 / 95
» A Parallel Hardware Architecture for Image Feature Detection
Sort
View
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
14 years 3 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
EUROCAST
2003
Springer
130views Hardware» more  EUROCAST 2003»
14 years 1 months ago
A Model of Neural Inspiration for Local Accumulative Computation
This paper explores the computational capacity of a novel local computational model that expands the conventional analogical and logical dynamic neural models, based on the charge ...
José Mira, Miguel Angel Fernández, M...
ICECCS
2002
IEEE
93views Hardware» more  ICECCS 2002»
14 years 1 months ago
Mnemosyne: Designing and Implementing Network Short-Term Memory
Network traffic logs play an important role in incident analysis. With the increasing throughput of network links, maintaining a complete log of all network activity has become a...
Giovanni Vigna, Andrew Mitchel
DSD
2004
IEEE
136views Hardware» more  DSD 2004»
14 years 11 days ago
FPGA Based Design of the Railway's Interlocking Equipments
This paper describes the architecture of a safety system of the railway's interlocking equipment, which has been developed for Czech railways. The system will be used for the...
Radek Dobias, Hana Kubatova
IEEEPACT
2005
IEEE
14 years 2 months ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun