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» A Parallel Hardware Architecture for Image Feature Detection
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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 5 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
14 years 2 months ago
A quantitative analysis of the speedup factors of FPGAs over processors
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vis...
ISVC
2009
Springer
14 years 3 months ago
Focused Volumetric Visual Hull with Color Extraction
Abstract. This paper introduces a new approach for volumetric visual hull reconstruction, using a voxel grid that focuses on the moving target object. This grid is continuously upd...
Daniel Knoblauch, Falko Kuester
AICCSA
2006
IEEE
101views Hardware» more  AICCSA 2006»
14 years 2 months ago
Refactoring Tools and Complementary Techniques
Poorly designed software systems are difficult to understand and maintain. Modifying code in one place could lead to unwanted repercussions elsewhere due to high coupling. Adding ...
Martin Drozdz, Derrick G. Kourie, Bruce W. Watson,...
IJPRAI
2002
97views more  IJPRAI 2002»
13 years 8 months ago
Shape Description and Invariant Recognition Employing Connectionist Approach
This paper presents a new approach for shape description and invariant recognition by geometric-normalization implemented by neural networks. The neural system consists of a shape...
Jezekiel Ben-Arie, Zhiqian Wang