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» A Parallel Packet Screen for High Speed Networks
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ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
13 years 11 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...
FCCM
2004
IEEE
141views VLSI» more  FCCM 2004»
13 years 11 months ago
Deep Packet Filter with Dedicated Logic and Read Only Memories
Searching for multiple string patterns in a stream of data is a computationally expensive task. The speed of the search pattern module determines the overall performance of deep p...
Young H. Cho, William H. Mangione-Smith
USENIX
2001
13 years 9 months ago
Flexible Control of Parallelism in a Multiprocessor PC Router
SMP Click is a software router that provides both flexibility and high performance on stock multiprocessor PC hardware. It achieves high performance using device, buffer, and queu...
Benjie Chen, Robert Morris
PVLDB
2010
166views more  PVLDB 2010»
13 years 6 months ago
Complex Event Detection at Wire Speed with FPGAs
Complex event detection is an advanced form of data stream processing where the stream(s) are scrutinized to identify given event patterns. The challenge for many complex event pr...
Louis Woods, Jens Teubner, Gustavo Alonso
CN
2006
124views more  CN 2006»
13 years 7 months ago
Packet classification using diagonal-based tuple space search
Multidimensional packet classification has attracted considerable research interests in the past few years due to the increasing demand on policy based packet forwarding and secur...
Fu-Yuan Lee, Shiuh-Pyng Shieh