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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 4 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ERSHOV
2006
Springer
13 years 11 months ago
Streaming Networks for Coordinating Data-Parallel Programs
A new coordination language for distributed data-parallel programs is presented, call SNet. The intention of SNet is to introduce advanced structuring techniques into a coordinatio...
Clemens Grelck, Sven-Bodo Scholz, Alexander V. Sha...
ICES
2000
Springer
140views Hardware» more  ICES 2000»
13 years 11 months ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
IOR
2007
106views more  IOR 2007»
13 years 7 months ago
Planning and Scheduling by Logic-Based Benders Decomposition
We combine mixed integer linear programming (MILP) and constraint programming (CP) to solve an important class of planning and scheduling problems. Tasks are allocated to faciliti...
John N. Hooker
IWRIDL
2006
ACM
141views Education» more  IWRIDL 2006»
14 years 1 months ago
Shallow syntax analysis in Sanskrit guided by semantic nets constraints
We present the state of the art of a computational platform for the analysis of classical Sanskrit. The platform comprises modules for phonology, morphology, segmentation and shal...
Gérard P. Huet