239 search results - page 24 / 48 » A Performance Evaluation of the Convex SPP-1000 Scalable Sha... |
ICPP
1990
IEEE
13 years 11 months ago
1990
IEEE
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
Increased complexity of memory systems to ameliorate the gap between the speed of processors and memory has made it increasingly harder for compilers to optimize an arbitrary code...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
The increasing demand for computational cycles is being met by the use of multi-core processors. Having large number of cores per node necessitates multi-core aware designs to ext...
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
Deterministic replay systems record and reproduce the execution of a hardware or software system. In contrast to replaying execution on uniprocessors, deterministic replay on mult...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Transactional Memory (TM) simplifies parallel programming by supporting atomic and isolated execution of user-identified tasks. To date, TM programming has required the use of l...