Sciweavers

204 search results - page 12 / 41
» A Pipelined Memory Architecture for High Throughput Network ...
Sort
View
ARC
2009
Springer
241views Hardware» more  ARC 2009»
14 years 2 months ago
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm
As the need for information security increases in our everyday life, the job of encoding/decoding for secure information delivery becomes a critical issue in data network systems. ...
Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro
EMSOFT
2008
Springer
13 years 9 months ago
Energy efficient streaming applications with guaranteed throughput on MPSoCs
In this paper we present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The ...
Jun Zhu, Ingo Sander, Axel Jantsch
JSAC
2006
172views more  JSAC 2006»
13 years 7 months ago
A Memory-Efficient Parallel String Matching Architecture for High-Speed Intrusion Detection
The ability to inspect both packet headers and payloads to identify attack signatures makes network intrusion detection system (NIDS) a promising approach to protect Internet syste...
Hongbin Lu, Kai Zheng, Bin Liu, Xin Zhang, Y. Liu
INFOCOM
2007
IEEE
14 years 1 months ago
TriBiCa: Trie Bitmap Content Analyzer for High-Speed Network Intrusion Detection
Abstract—Deep packet inspection (DPI) is often used in network intrusion detection and prevention systems (NIDPS), where incoming packet payloads are compared against known attac...
N. Sertac Artan, H. Jonathan Chao
CCGRID
2011
IEEE
12 years 11 months ago
High Performance Pipelined Process Migration with RDMA
—Coordinated Checkpoint/Restart (C/R) is a widely deployed strategy to achieve fault-tolerance. However, C/R by itself is not capable enough to meet the demands of upcoming exasc...
Xiangyong Ouyang, Raghunath Rajachandrasekar, Xavi...