204 search results - page 9 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
CF
2004
ACM
14 years 29 days ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
CF
2008
ACM
13 years 9 months ago
2008
ACM
To meet growing terabit link rates, highly parallel and scalable architectures are needed for IP lookup engines in next generation routers. This paper proposes an SRAM-based multi...
SIPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
IPPS
2008
IEEE
14 years 1 months ago
2008
IEEE
Pipelined SRAM-based algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high throughput IP lookup. Multiple pipelines c...