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CGO
2008
IEEE
14 years 2 months ago
Prediction and trace compression of data access addresses through nested loop recognition
This paper describes an algorithm that takes a trace (i.e., a sequence of numbers or vectors of numbers) as input, and from that produces a sequence of loop nests that, when run, ...
Alain Ketterlin, Philippe Clauss
AVI
2004
13 years 9 months ago
Integrating expanding annotations with a 3D explosion probe
Understanding complex 3D virtual models can be difficult, especially when the model has interior components not initially visible and ancillary text. We describe new techniques fo...
Henry Sonnet, M. Sheelagh T. Carpendale, Thomas St...
EMSOFT
2010
Springer
13 years 5 months ago
From high-level component-based models to distributed implementations
Constructing correct distributed systems from their high-level models has always been a challenge and often subject to serious errors because of their non-deterministic and non-at...
Borzoo Bonakdarpour, Marius Bozga, Mohamad Jaber, ...
FPL
2009
Springer
107views Hardware» more  FPL 2009»
14 years 8 days ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...
STORAGESS
2005
ACM
14 years 1 months ago
An electric fence for kernel buffers
Improper access of data buffers is one of the most common errors in programs written in assembler, C, C++, and several other languages. Existing programs and OSs frequently acces...
Nikolai Joukov, Aditya Kashyap, Gopalan Sivathanu,...