543 search results - page 74 / 109 » A Randomized Parallel Sorting Algorithm with an Experimental... |
IPPS
2002
IEEE
14 years 17 days ago
2002
IEEE
In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of cl...
IJHPCA
2006
13 years 7 months ago
2006
Today, large scale parallel systems are available at relatively low cost. Many powerful such systems have been installed all over the world and the number of users is always incre...
IPPS
2008
IEEE
14 years 2 months ago
2008
IEEE
The Sony-Toshiba-IBM Cell Broadband Engine is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD coprocessing units (SPEs) ...
SPAA
2010
ACM
14 years 14 days ago
2010
ACM
In this paper we study a dynamic version of capacity maximization in the physical model of wireless communication. In our model, requests for connections between pairs of points i...
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...