In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...
Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici,...
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Grid technologies are becoming more and more mature in recent years. In contrast to this trend, the resource measurement landscape in Grids looks rather dismal. As part of ChinaGri...
Weimin Zheng, Meizhi Hu, Lin Liu, Yongwei Wu, Jing...
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
Abstract— Remote Direct Memory Access (RDMA) and pointto-point network fabrics both have their own advantages. MPI middleware implementations typically use one or the other, howe...