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ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
14 years 1 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
IPPS
2006
IEEE
14 years 1 months ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
14 years 2 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
IPPS
1998
IEEE
13 years 12 months ago
Efficient Runtime Thread Management for the Nano-Threads Programming Model
Abstract. The nano-threads programming model was proposed to effectively integrate multiprogramming on shared-memory multiprocessors, with the exploitation of fine-grain parallelis...
Dimitrios S. Nikolopoulos, Eleftherios D. Polychro...
ICNC
2005
Springer
14 years 1 months ago
A Multi-cluster Grid Enabled Evolution Framework for Aerodynamic Airfoil Design Optimization
Advances in grid computing have recently sparkled the research and development of Grid problem solving environments for complex design. Parallelism in the form of distributed compu...
Hee-Khiang Ng, Dudy Lim, Yew-Soon Ong, Bu-Sung Lee...