317 search results - page 10 / 64 » A Scalable Architecture for Montgomery Multiplication |
ICDE
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper we introduce a new architectural design of a large scale distributed stream processing system. The system adopts a two layer architecture. Based on the locality and ...
RECONFIG
2008
IEEE
14 years 1 months ago
2008
IEEE
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
This paper presents SPA (Simple Power Analysis) attacks against public-key cryptosystems implemented on an FPGA platform. The SPA attack investigates a power waveform generated by...
RTAS
1997
IEEE
13 years 11 months ago
1997
IEEE
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
ISCAPDCS
2004
13 years 9 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...