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» A Semantics for Multiprocessor Systems
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143
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IPPS
2007
IEEE
15 years 10 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
151
Voted
ESTIMEDIA
2007
Springer
15 years 9 months ago
Run-time Task Overlapping on Multiprocessor Platforms
Today’s embedded applications often consist of multiple concurrent tasks. These tasks are decomposed into subtasks which are in turn assigned and scheduled on multiple different...
Zhe Ma, Daniele Paolo Scarpazza, Francky Catthoor
124
Voted
LCPC
2007
Springer
15 years 9 months ago
Communicating Multiprocessor-Tasks
The use of multiprocessor tasks (M-tasks) has been shown to be successful for mixed task and data parallel implementations of algorithms from scientific computing. The approach o...
Jörg Dümmler, Thomas Rauber, Gudula R&uu...
137
Voted
ICPADS
2006
IEEE
15 years 9 months ago
Accuracy versus Migration Overhead in Real-Time Multiprocessor Reweighting Algorithms
We consider schemes for enacting task share changes—a process called reweighting—on real-time multiprocessor platforms. Our particular focus is reweighting schemes that are de...
Aaron Block, James H. Anderson
145
Voted
IEEEPACT
2005
IEEE
15 years 9 months ago
Characterization of TCC on Chip-Multiprocessors
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi...