Sciweavers

7452 search results - page 139 / 1491
» A Semantics for Multiprocessor Systems
Sort
View
EUROPAR
2008
Springer
15 years 5 months ago
Performance Implications of Cache Affinity on Multicore Processors
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity i...
Vahid Kazempour, Alexandra Fedorova, Pouya Alagheb...
CDES
2008
166views Hardware» more  CDES 2008»
15 years 5 months ago
Scalable Directory Organization for Tiled CMP Architectures
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
Alberto Ros, Manuel E. Acacio, José M. Garc...
138
Voted
ETS
2010
IEEE
130views Hardware» more  ETS 2010»
15 years 4 months ago
A distributed architecture to check global properties for post-silicon debug
Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking g...
Erik Larsson, Bart Vermeulen, Kees Goossens
JPDC
2006
92views more  JPDC 2006»
15 years 3 months ago
A tight bound on remote reference time complexity of mutual exclusion in the read-modify-write model
In distributed shared memory multiprocessors, remote memory references generate processor-to-memory traffic, which may result in a bottleneck. It is therefore important to design ...
Sheng-Hsiung Chen, Ting-Lu Huang
IPPS
2010
IEEE
15 years 1 months ago
A general algorithm for detecting faults under the comparison diagnosis model
We develop a widely applicable algorithm to solve the fault diagnosis problem in certain distributed-memory multiprocessor systems in which there are a limited number of faulty pr...
Iain A. Stewart