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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 4 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
STACS
2009
Springer
14 years 2 months ago
Approximating Acyclicity Parameters of Sparse Hypergraphs
The notions of hypertree width and generalized hypertree width were introduced by Gottlob, Leone, and Scarcello in order to extend the concept of hypergraph acyclicity. These noti...
Fedor V. Fomin, Petr A. Golovach, Dimitrios M. Thi...
STOC
2007
ACM
134views Algorithms» more  STOC 2007»
14 years 8 months ago
Hardness of routing with congestion in directed graphs
Given as input a directed graph on N vertices and a set of source-destination pairs, we study the problem of routing the maximum possible number of source-destination pairs on pat...
Julia Chuzhoy, Venkatesan Guruswami, Sanjeev Khann...
IICS
2003
Springer
14 years 1 months ago
Where to Start Browsing the Web?
Both human users and crawlers face the problem of finding good start pages to explore some topic. We show how to assist in qualifying pages as start nodes by link-based ranking al...
Dániel Fogaras
SIAMDM
2008
119views more  SIAMDM 2008»
13 years 7 months ago
On the Graph Bisection Cut Polytope
Given a graph G = (V, E) with node weights v N {0}, v V , and some number F N{0}, the convex hull of the incidence vectors of all cuts (S), S V with (S) F and (V \ S) F is ...
Michael Armbruster, Christoph Helmberg, Marzena F&...