323 search results - page 45 / 65 » A Survey of Automated Techniques for Formal Software Verific... |
CODES
2008
IEEE
13 years 9 months ago
2008
IEEE
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
IIWAS
2008
13 years 9 months ago
2008
In a service-oriented architecture, systems communicate by exchanging messages. In this work, we propose a formal model based on OCL-constrained UML Class diagrams and a methodolo...
ISESE
2005
IEEE
14 years 1 months ago
2005
IEEE
Many risk specific concepts like “threat”, “consequence” and “risk” belong to the daily language. In a risk analysis one cannot be certain that the participants’ int...
SIGSOFT
2002
ACM
14 years 8 months ago
2002
ACM
Security is a very important issue in information processing, especially in open network environments like the Internet. The Common Criteria (CC) is the standard requirements cata...
IPPS
2010
IEEE
13 years 4 months ago
2010
IEEE
Abstract--Ensuring the correctness of complex implementations of software transactional memory (STM) is a daunting task. Attempts have been made to formally verify STMs, but these ...