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» A System Level Resource Estimation Tool for FPGAs
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ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 6 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
SCAM
2008
IEEE
14 years 5 months ago
CoordInspector: A Tool for Extracting Coordination Data from Legacy Code
—More and more current software systems rely on non trivial coordination logic for combining autonomous services typically running on different platforms and often owned by diffe...
Nuno F. Rodrigues, Luís Soares Barbosa
VTC
2008
IEEE
14 years 5 months ago
Resource Allocation and Control Signaling in the WINNER Flexible MAC Concept
—The EU WINNER projects have studied OFDM-based packet data systems beyond 3G that use adaptivity on all timescales to obtain high flexibility and performance. The adaptive trans...
Mikael Sternad, Tommy Svensson, Martin Döttli...
IPPS
2007
IEEE
14 years 5 months ago
Virtual Execution Environments: Support and Tools
In today’s dynamic computing environments, the available resources and even underlying computation engine can change during the execution of a program. Additionally, current tre...
Apala Guha, Jason Hiser, Naveen Kumar, Jing Yang, ...
CIKM
2008
Springer
14 years 26 days ago
SNIF TOOL: sniffing for patterns in continuous streams
Continuous time-series sequence matching, specifically, matching a numeric live stream against a set of predefined pattern sequences, is critical for domains ranging from fire spr...
Abhishek Mukherji, Elke A. Rundensteiner, David C....