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» A System Level Resource Estimation Tool for FPGAs
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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 4 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
MIR
2004
ACM
242views Multimedia» more  MIR 2004»
14 years 4 months ago
Content based access for a massive database of human observation video
We present in this paper a CBIR system for use in a psychological study of the relationship between human movement and Dyslexia. The system allows access to up to 500 hours of vid...
Laurent Joyeux, Erika Doyle, Hugh Denman, Andrew C...
TOMS
1998
148views more  TOMS 1998»
13 years 10 months ago
PELLPACK: A Problem-Solving Environment for PDE-Based Applications on Multicomputer Platforms
This paper presents the software architecture and implementation of the problem solving environment (PSE) PELLPACK for modeling physical objects described by partial differential ...
Elias N. Houstis, John R. Rice, Sanjiva Weerawaran...
BICA
2010
13 years 5 months ago
Explanatory Aspirations and the Scandal of Cognitive Neuroscience
In this position paper we argue that BICA must simultaneously be compatible with the explanation of human cognition and support the human design of artificial cognitive systems. Mo...
Ross Gayler, Simon D. Levy, Rens Bod
BROADNETS
2004
IEEE
14 years 2 months ago
The Effects of the Sub-Carrier Grouping on Multi-Carrier Channel Aware Scheduling
Channel-aware scheduling and link adaptation (LA) methods are widely considered to be crucial for realizing high data rates in wireless networks. Multi-carrier systems that spread...
Fanchun Jin, Gokhan Sahin, Amrinder Arora, Hyeong-...