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ACSD
2004
IEEE
113views Hardware» more  ACSD 2004»
13 years 11 months ago
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of...
Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
ISCAS
2005
IEEE
144views Hardware» more  ISCAS 2005»
14 years 1 months ago
Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis
— Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the...
M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter K...
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
13 years 12 months ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...
RTSS
1998
IEEE
13 years 11 months ago
A Dynamic Quality of Service Middleware Agent for Mediating Application Resource Usage
High-bandwidth applications with time-dependent resource requirements demand certain resource level assurances in order to operate correctly. Quality of Service resource managemen...
Scott A. Brandt, Gary J. Nutt, Toby Berk, James E....
ICRA
2007
IEEE
143views Robotics» more  ICRA 2007»
14 years 1 months ago
Anytime, Dynamic Planning in High-dimensional Search Spaces
— We present a sampling-based path planning and replanning algorithm that produces anytime solutions. Our algorithm tunes the quality of its result based on available search time...
Dave Ferguson, Anthony Stentz