209 search results - page 9 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
IPPS
2002
IEEE
14 years 19 days ago
2002
IEEE
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog ...
DT
2007
13 years 7 months ago
2007
This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fano...
GLVLSI
1998
IEEE
13 years 12 months ago
1998
IEEE
In this paper we introduce a VLSI priority encoder that uses a novel priority lookahead scheme to reduce the delay for the worse case operation of the circuit, while maintaining a...
GLVLSI
2002
IEEE
14 years 20 days ago
2002
IEEE
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...