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SAMOS
2007
Springer
14 years 1 months ago
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
Nainesh Agarwal, Nikitas J. Dimopoulos
IEEEPACT
2006
IEEE
14 years 1 months ago
Program generation for the all-pairs shortest path problem
A recent trend in computing are domain-specific program generators, designed to alleviate the effort of porting and reoptimizing libraries for fast-changing and increasingly com...
Sung-Chul Han, Franz Franchetti, Markus Püsch...
IPPS
2006
IEEE
14 years 1 months ago
Acceleration of a content-based image-retrieval application on the RDISK cluster
Because of the growing use of multimedia content over Internet, Content-Based Image Retrieval (CBIR) has recently received a lot of interest. While accurate search techniques base...
Auguste Noumsi, Steven Derrien, Patrice Quinton
ISCAS
2005
IEEE
144views Hardware» more  ISCAS 2005»
14 years 1 months ago
Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis
— Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the...
M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter K...
ACMMSP
2004
ACM
125views Hardware» more  ACMMSP 2004»
14 years 1 months ago
Improving trace cache hit rates using the sliding window fill mechanism and fill select table
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
Muhammad Shaaban, Edward Mulrane