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» A Temporal Logic of Robustness
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DAC
2007
ACM
14 years 9 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
ICDT
2009
ACM
248views Database» more  ICDT 2009»
14 years 9 months ago
Automatic verification of data-centric business processes
We formalize and study business process systems that are centered around "business artifacts", or simply "artifacts". This approach focuses on data records, kn...
Alin Deutsch, Richard Hull, Fabio Patrizi, Victor ...
POPL
2005
ACM
14 years 9 months ago
Synthesis of interface specifications for Java classes
While a typical software component has a clearly specified (static) interface in terms of the methods and the input/output types they support, information about the correct sequen...
P. Madhusudan, Pavol Cerný, Rajeev Alur, Wo...
POPL
2005
ACM
14 years 9 months ago
Transition predicate abstraction and fair termination
on Predicate Abstraction and Fair Termination Andreas Podelski Andrey Rybalchenko Max-Planck-Institut f?ur Informatik Saarbr?ucken, Germany Predicate abstraction is the basis of m...
Andreas Podelski, Andrey Rybalchenko
POPL
2003
ACM
14 years 9 months ago
From symptom to cause: localizing errors in counterexample traces
There is significant room for improving users' experiences with model checking tools. An error trace produced by a model checker can be lengthy and is indicative of a symptom...
Thomas Ball, Mayur Naik, Sriram K. Rajamani