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» A Two-Phase Process for Software Architecture Improvement
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144
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IPPS
2006
IEEE
15 years 9 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
128
Voted
SEFM
2005
IEEE
15 years 9 months ago
Formalising Control in Robust Spoken Dialogue Systems
The spoken language interface is now becoming an increasingly serious research topic with application to a wide range of highly engineered systems. Such systems not only include i...
Hui Shi, Robert J. Ross, John A. Bateman
208
Voted
SIGCOMM
1995
ACM
15 years 7 months ago
Performance Analysis of MD5
MD5 is an authentication algorithm proposed as the required implementation of the authentication option in IPv6. This paper presents an analysis of the speed at which MD5 can be i...
Joseph D. Touch
133
Voted
UIST
2010
ACM
15 years 1 months ago
Soylent: a word processor with a crowd inside
This paper introduces architectural and interaction patterns for integrating crowdsourced human contributions directly into user interfaces. We focus on writing and editing, compl...
Michael S. Bernstein, Greg Little, Robert C. Mille...
HPCA
2009
IEEE
16 years 4 months ago
Variation-aware dynamic voltage/frequency scaling
Fine-grained dynamic voltage/frequency scaling (DVFS) is an important tool in managing the balance between power and performance in chip-multiprocessors. Although manufacturing pr...
Sebastian Herbert, Diana Marculescu