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» A Unified Architectural Tradeoff Methodology
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ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
14 years 1 months ago
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
14 years 6 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik
SAMOS
2005
Springer
14 years 3 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
IFIP
2001
Springer
14 years 2 months ago
An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms
: One of the most important problems in SOC platforms design is that of defining strategies for tuning the parameters of a parameterized system so as to obtain the Pareto-optimal s...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 6 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...