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» A Unified Architectural Tradeoff Methodology
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ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 6 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
HPCA
1998
IEEE
14 years 1 months ago
Speculative Versioning Cache
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
Sridhar Gopal, T. N. Vijaykumar, James E. Smith, G...
CLEIEJ
2006
169views more  CLEIEJ 2006»
13 years 9 months ago
Tailoring RUP for LMS Selection: A Case Study
Learning Management System (LMS) development has become a high priority project for educational institutions and organizations, as it provides the virtual environment for online e...
Luis Eduardo Mendoza, María A. Pérez...
CODES
2002
IEEE
14 years 2 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
14 years 1 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan