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» A Unified Architectural Tradeoff Methodology
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CORR
2006
Springer
112views Education» more  CORR 2006»
13 years 9 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...
DATE
2007
IEEE
142views Hardware» more  DATE 2007»
14 years 4 months ago
Optimizing instruction-set extensible processors under data bandwidth constraints
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Way...
DAC
2004
ACM
14 years 10 months ago
Defect tolerant probabilistic design paradigm for nanotechnologies
Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the trem...
Margarida F. Jacome, Chen He, Gustavo de Veciana, ...
CSE
2008
IEEE
13 years 11 months ago
Application Specific Processors for Multimedia Applications
A well-known challenge during processor design is to obtain best possible results for a typical target application domain by combining flexibility and computational performance. A...
Rashid Muhammad, Ludovic Apvrille, Renaud Pacalet
ICMCS
1995
IEEE
156views Multimedia» more  ICMCS 1995»
14 years 1 months ago
Spatio-Temporal Modeling of Video Data for On-Line Object-Oriented Query Processing
This paper presents a framework for data modeling ntic abstraction of image/video data. The framework is based on spatio-temporalinformation associated with salient objects in an ...
Young Francis Day, Serhan Dagtas, Mitsutoshi Iino,...