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HPCA
2011
IEEE
12 years 11 months ago
ACCESS: Smart scheduling for asymmetric cache CMPs
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishanka...
IM
2003
13 years 9 months ago
Facilitating Efficient and Reliable Monitoring through HAMSA
: Monitoring is a fundamental building block of any network management system. It is needed to ensure that the network operates within the required parameters, and to account for u...
David Breitgand, Danny Dolev, Danny Raz, Gleb Shav...
ICPR
2002
IEEE
14 years 9 months ago
Integrated Event Recognition from Multiple Sources
This paper proposes a system architecture for event recognition that integrates information from multiple sources (e.g., gesture and speech recognition from distributed sensors in...
Hiroaki Kawashima, Takashi Matsuyama
EUROMICRO
2004
IEEE
13 years 11 months ago
An Experimental Framework for Testing Web Prefetching Techniques
The popularity of web objects, and by extension the popularity of the web sites, besides the appearance of clear footprints in user's accesses that show a considerable spatia...
Josep Domènech, Ana Pont, Julio Sahuquillo,...
IPPS
2010
IEEE
13 years 6 months ago
On the parallelisation of MCMC by speculative chain execution
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
Jonathan M. R. Byrd, Stephen A. Jarvis, Abhir H. B...