121 search results - page 7 / 25 » A cell-based power estimation in CMOS combinational circuits |
DAC
1996
ACM
13 years 11 months ago
1996
ACM
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
CICC
2011
12 years 7 months ago
2011
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...