1008 search results - page 60 / 202 » A cis-regulatory logic simulator |
WSC
1997
13 years 10 months ago
1997
This paper investigates an attempt to combine different simulation tools in order to build a simulation environment that can be used to model complex system behaviour. The compone...
ICCAD
1999
IEEE
14 years 1 months ago
1999
IEEE
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
ISLPED
1995
ACM
14 years 8 days ago
1995
ACM
When estimating the dynamic power dissipated by a circuit di erent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as ...
WSC
2004
13 years 10 months ago
2004
In standard optimistic parallel event simulation, no restriction exists on the maximum lag in simulation time between the fastest and slowest logical processes (LPs). Overoptimist...
TC
1998
13 years 8 months ago
1998
—This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs)...