1008 search results - page 63 / 202 » A cis-regulatory logic simulator |
ENTCS
2006
13 years 8 months ago
2006
A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described. Compilation is by mechanised proof in t...
ENTCS
2007
13 years 8 months ago
2007
Many programming calculi have been designed to have a Curry-Howard correspondence with a classical logic. We investigate the effect that different choices of logical connective ha...
VLSID
2007
IEEE
14 years 9 months ago
2007
IEEE
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
ANSS
2003
IEEE
14 years 2 months ago
2003
IEEE
In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate a...