479 search results - page 67 / 96 » A clustering technique to optimize hardware software synchro... |
SPAA
2009
ACM
14 years 8 months ago
2009
ACM
Transactional memory (TM) eliminates many problems associated with lock-based synchronization. Over recent years, much progress has been made in software and hardware implementati...
FPGA
2009
ACM
14 years 2 months ago
2009
ACM
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
DSN
2007
IEEE
14 years 2 months ago
2007
IEEE
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
ICS
1999
Tsinghua U.
13 years 12 months ago
1999
Tsinghua U.
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...