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» A comparative study of power efficient SRAM designs
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ISQED
2009
IEEE
115views Hardware» more  ISQED 2009»
14 years 2 months ago
TuneLogic: Post-silicon tuning of dual-Vdd designs
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. It is our thesis that variability should be addres...
Stephen Bijansky, Sae Kyu Lee, Adnan Aziz
GLVLSI
2010
IEEE
310views VLSI» more  GLVLSI 2010»
14 years 17 days ago
Graphene tunneling FET and its applications in low-power circuit design
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Moh...
ICIP
2008
IEEE
14 years 2 months ago
Design and performance of a novel low-density parity-check code for distributed video coding
Low-density parity-check (LDPC) codes are nowadays one of the hottest topics in coding theory, notably due to their advantages in terms of bit error rate performance and low compl...
João Ascenso, Catarina Brites, Fernando Per...
UIC
2007
Springer
14 years 1 months ago
Maximizing Network Lifetime Under Reliability Constraints Using a Cross-Layer Design in Dense Wireless Sensor Networks
Abstract. Recent experimental studies have shown that radio links between low-power devices are extremely unreliable. In particular, the instability and unpredictability of low-pow...
Shan Guo Quan, Young Yong Kim
BMCBI
2008
121views more  BMCBI 2008»
13 years 8 months ago
Stability of gene contributions and identification of outliers in multivariate analysis of microarray data
Background: Multivariate ordination methods are powerful tools for the exploration of complex data structures present in microarray data. These methods have several advantages com...
Florent Baty, Daniel Jaeger, Frank Preiswerk, Mart...