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» A computational architecture for heterogeneous reasoning
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IEEEPACT
2006
IEEE
14 years 4 months ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
SG
2005
Springer
14 years 3 months ago
From Artefact Representation to Information Visualisation: Genesis of Informative Modelling
Abstract. In the field of the architectural heritage, the representation of artefacts, particularly for communication purposes, has benefited from the development of computer-based...
Iwona Dudek, Jean-Yves Blaise
IFL
2004
Springer
138views Formal Methods» more  IFL 2004»
14 years 3 months ago
A Rational Deconstruction of Landin's SECD Machine
Landin’s SECD machine was the first abstract machine for the λ-calculus viewed as a programming language. Both theoretically as a model of computation and practically as an ide...
Olivier Danvy
LCN
2003
IEEE
14 years 3 months ago
Assuring Fair Allocation of Excess Bandwidth in Reservation Based Core-Stateless Networks
Assuring guaranteed services and providing fair bandwidth sharing are much sought characteristics in the current network architecture research. The IntServ approaches achieve thos...
Avadora Dumitrescu, Jarmo Harju
ASPLOS
1994
ACM
14 years 2 months ago
Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations
There is an increasing trend to use commodity microprocessors as the compute engines in large-scale multiprocessors. However, given that the majority of the microprocessors are so...
James Laudon, Anoop Gupta, Mark Horowitz